1. Field of the Invention
The present invention relates to a non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Many types of EEPROM and flash memories utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series, sandwiched between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to source line 128. Select gate 120 is controlled by applying the appropriate voltages to select line SGD. Select gate 122 is controlled by applying the appropriate voltages to select line SGS. Each of the transistors 100, 102, 104 and 106 has a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Note that although FIGS. 1 and 2 shows four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 202, 204 and 206 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors (also called gates) and four memory cells. For example, NAND string 202 includes select transistors 220 and 230, and memory cells 222, 224, 226 and 228. NAND string 204 includes select transistors 240 and 250, and memory cells 242, 244, 246 and 248. Each NAND string is connected to the source line by its source select gate (e.g. select transistor 230 and select transistor 250). A selection line SGS is used to control the source select gates (e.g., 230 and 250).
The various NAND strings are connected to respective bit lines by select transistors 220, 240, etc., which are controlled by select line SGD. Each bit line and the respective NAND string(s) that are connected to that bit line via a bit line contact comprise the columns of the array of memory cells. Bit lines are shared with multiple NAND strings. Typically, the bit line runs on top of the NAND strings in a direction perpendicular to the word lines and is connected to one or more sense amplifiers.
The word lines (WL3, WL2, WL1 and WL0) comprise the rows of the array. Word line WL3 is connected to the control gates for memory cell 222 and memory cell 242. Word line WL2 is connected to the control gates for memory cell 224, memory cell 244 and memory cell 252. Word line WL1 is connected to the control gates for memory cell 226 and memory cell 246. Word line WL0 is connected to the control gates for memory cell 228 and memory cell 248.
Each memory cell can store data (analog or digital). When storing one bit of digital data (referred to as a binary memory cell), the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after programming is positive and defined as logic “0.” When the threshold voltage is negative and a read is attempted by applying 0 volts to the control gate, the memory cell will turn on to indicate logic one is being stored. When the threshold voltage is positive and a read operation is attempted by applying 0 volts to the control gate, the memory cell will not turn on, which indicates that logic zero is stored.
A memory cell can also store multiple levels of information (referred to as a multi-state memory cell). In the case of storing multiple levels of data, the range of possible threshold voltages is divided into the number of levels of data. For example, if four levels of information is stored, there will be four threshold voltage ranges assigned to the data values “11”, “10”, “01”, and “00.” In one example of a NAND type memory, the threshold voltage after an erase operation is negative and defined as “11”. Positive threshold voltages are used for the states of “10”, “01”, and “00.”
Relevant examples of NAND type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference: U.S. Pat. Nos. 5,570,315; 5,774,397; 6,046,935; 6,456,528; and U.S. Pat. Publication No. US2003/0002348. The discussion herein can also apply to other types of flash memory in addition to NAND as well as other types of non-volatile memory.
When programming a flash memory cell, a program voltage is applied to the control gate and the bit line is grounded. Due to the voltage differential between the channel of the flash memory cell and the floating gate, electrons from the channel area under the floating gate are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised. To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one memory cell in each of the other NAND strings that utilize the same word line. For example, when programming memory cell 224 of FIG. 3, the program voltage will also be applied to the control gate of memory cell 244 because both memory cells share the same word line. A problem arises when it's desired to program one cell on a word line without programming other cells connected to the same word line, for example, when it's desired to program memory cell 224 and not memory cell 244. Because the program voltage is applied to all memory cells connected to a word line, an unselected memory cell (a memory cell that is not to be programmed) on the same word line may become inadvertently programmed. For example, memory cell 244 is adjacent to memory cell 224. When programming memory cell 224, there is a concern that memory cell 244 might unintentionally be programmed. The unintentional programming of the unselected memory cell on the selected word line is referred to as “program disturb.”
Several techniques can be employed to prevent program disturb. In one method known as “self boosting,” the unselected NAND strings are electrically isolated from the corresponding bit lines and a pass voltage (e.g. 7-10 volts, but not limited to this range) is applied to the unselected word lines during programming. The unselected word lines couple to the channel area of the unselected NAND strings, causing a voltage (e.g., 6-10 volts) to exist in the channel of the unselected NAND strings, thereby reducing program disturb. Self boosting causes a boosted voltage to exist in the channel which lowers the voltage differential across the tunnel oxide and hence reduces program disturb. Note that the boosted channel voltage can vary largely since the boosted channel voltage depends on the value of the pass voltage and also on the state of the memory cells, with boosting being most efficient (highest channel voltage) when all memory cells in the NAND string are in the erased state.
FIGS. 4 and 5 depict NAND strings that are being programmed and inhibited using the self-boosting method. FIG. 4 depicts a NAND string being programmed. The NAND string of FIG. 4 includes eight memory cells 304, 306, 308, 310, 312, 314, 316 and 318. Each of those eight memory cells includes a floating gate (FG) and a control gate (CG). Between each of the floating gates are source/drain regions 330. In some implementations, there is a P-type substrate (e.g., Silicon), an N-well within the substrate and a P-well within the N-well (all of which are not depicted to make the drawings more readable). Note that the P-well may contain a so called channel implantation that is usually a P-type implantation that determines or helps to determine the threshold voltage and other characteristics of the memory cells. The source/drain regions 330 are N+ diffusion regions that are formed in the P-well.
At one end of the NAND string is a drain side select gate 324. The drain select gate 324 connects the NAND string to the corresponding bit line via bit line contact 334. At another end of the NAND string is a source select gate 322. Source select gate 322 connects the NAND string to common source line 332. During programming, the memory cell selected for programming (e.g., memory cell 312) receives a program voltage Vpgm on its associated word line. The program voltage Vpgm can typically vary between 12 to 24 volts. In one embodiment, the program voltage signal is a set of pulses which increase in magnitude with each new pulse. A pass voltage Vpass of approximately 8 volts is applied to the control gates of the memory cells that are not selected for programming. Source select gate 322 is in an isolating state, receiving 0 volts at its gate (G). A low voltage is applied to the common source line 332. This low voltage can be zero volts. However, the source voltage can also be slightly higher than zero volts to provide better isolation characteristics of the source side select gate. A voltage Vsgd, which is typically in the range of the power supply voltage Vdd (e.g., 2.5 volts), is applied to drain side select gate 324. Zero volts is applied to bit line contact 334 via the corresponding bit line to enable programming of the selected memory cell 312. Channel 340 is at or close to zero volts. Because of the voltage differential between the channel and the floating gate of memory cell 314, electrons tunnel through the gate oxide (also commonly referred to as tunnel oxide) into the floating gate by Fowler-Nordheim tunneling.
The NAND string of FIG. 5 depicts a NAND string being inhibited from programming. The NAND string includes eight memory cells 350, 352, 354, 356, 358, 360, 362 and 364. The NAND string also includes drain select gate 366 connecting the NAND string to the corresponding bit line via bit line contact 374, and source select gate for 368 connecting the NAND string to common source line 332. Between each of the floating gate stacks are source/drain regions 370. The NAND string of FIG. 5 has Vsgd applied to the gate of the drain select gate 366, zero volts applied to the gate of the source side select gate 368 and zero volts (or a slightly higher voltage) at the common source line 332. Bit line contact 374 receives the power supply voltage Vdd via the corresponding bit line in order to inhibit the programming of memory cell 358.
When Vdd is applied, the drain select transistor 366 will initially be in a conducting state; therefore, the channel area under the NAND string will partly be charged up to a higher potential (higher than zero volts and typically equal or almost equal to Vdd). This charging is commonly referred to as pre-charging. The pre-charging will stop automatically when the channel potential has reached Vdd or a lower potential given by Vsgd−Vt, where Vt equals the threshold voltage of the drain select gate 366. In general, during pre-charging, Vsgd is chosen in such a way that Vsgd−Vt>Vdd so that the channel area under the NAND string can be pre-charged to Vdd. After the channel has reached that potential, the select gate transistor is non-conducting or made non-conducting by lowering Vsgd to a value similar to Vdd (e.g. 2.5 volts). Subsequently, the voltages Vpass and Vpgm are ramped up from zero volts to their respective final values (not necessarily at the same time), and because the drain side select gate transistor 366 is in a non-conducting state, the channel potential will start to rise because of the capacitive coupling between the word lines and the channel area. This phenomenon is called self boosting. It can be seen from FIG. 5 that channel 380 is boosted, more or less uniformly, to a boosting voltage. Because the voltage differential between the floating gate of memory cell 358 and channel 380 has been reduced, programming is inhibited. More information about programming NAND flash memory, including self boosting techniques, can be found in U.S. Pat. No. 6,859,397, “Source Side Self Boosting Technique for Non-Volatile Memory,” Lutze at al., incorporated herein by reference in its entirety.
Another attempt to address program disturb is Erased Area Self Boosting (“EASB”). EASB attempts to isolate the channel of previously programmed cells from the channel of the cell being inhibited. In the EASB method, the channel area of the selected NAND string is divided into two areas. An area at the source side of the selected word line that can contain a number of programmed (or erased cells) memory cells and an area at the drain side of the selected word line in which the cells are still in the erased state, or at least not yet in the final programmed state. The two areas are separated by a word line that is biased to a low voltage, typically zero volts. Because of this separation, the two areas can be boosted to different potentials. In almost all cases, the area at the drain side of the selected word line will be boosted to a higher potential than the area at the source side. Since the highest boosted area is the area with the erased cells, this boosting method is referred to as Erased Area Self Boosting (EASB).
Although the above boosting methods have reduced program disturb, they have not eliminated the problem. One effect that can occur to the memory cell next to the source select gate (e.g., memory cell 350 is next to source select gate 368 of FIG. 5) is Gate Induced Drain Leakage (GIDL), which is also referred to as Band-To-Band-Tunneling. GIDL causes the generation of electrons at the source select gate when the channel under the NAND string is inhibited from programming (boosted to a high voltage). Subsequently, the generated electrons are accelerated in the strong lateral electric field towards the floating gate of the memory cell next to the source select gate. Some of the electrons can gain sufficient energy to be injected into the tunnel oxide under the floating gate or in the floating gate itself and, thus modify the threshold voltage of the corresponding memory cell.
FIG. 6 shows a portion of the NAND string of FIG. 5, with a zooming-in on the drain and a portion of the channel for memory cell 350. Due to boosting of the NAND string during a program inhibit operation (for example when other NAND strings are being programmed), a high voltage is present in the channel area of the boosted NAND string (see boosted channel 380). This high voltage is also present at the junction area between source select gate 368, which is typically biased at 0V, and memory cell 350 next to source select gate 368. This bias condition may cause GIDL, which can result in the creation of electron hole pairs. The holes will go to P-well area 384. The electrons will move to the boosted channel area 380. In general, there is a lateral electric field present in the junction area between the source select gate and the memory cell next to the source side select gate because part of that junction (drain/source) is depleted due to the large voltage difference between channel area under the memory cells and the channel area under the select gate. The electrons can be accelerated in the electric field and may gain enough energy to be injected in the tunnel oxide of the memory cell next to the source side select gate or may even reach the floating gate of that memory cell. In both cases, the threshold voltage of the corresponding memory cell will change due to the presence of the injected electrons, thereby, risking an error when reading the memory cell next to the source select gate.
Thus, there is a need for a new mechanism to reduce the impact of program disturb.